1. Field of the Invention
The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to techniques for producing gate-level and structural descriptions used in a computer controlled EDA system for integrated circuit (IC) design.
2. Related Art
An electronic design automation (EDA) system is a form of computer aided design (CAD) system and is used for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this high level design language description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on library primitives. The generic netlist can be translated into a lower level technology-specific netlist based on a technology-specific library. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. A single node can have multiple fan-ins and multiple fan-outs. The netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. One result is a physical device layout in mask form which can be used to directly implement structures in silicon to realize the physical IC device.
FIG. 1 illustrates a typical design flow 10 for the design of integrated circuits (e.g., ASIC, microprocessors, microcontrollers, etc.). This IC design flow 10 requires several equivalent descriptions of the design library that are used as input to different CAD tools. In the prior art system 10, a set of hand-coded descriptions of low-level design cells is referred to as a "library." For instance, a simulation library 12 and a test library 22 are shown. Because these libraries 12 and 22 are hand-coded, significant effort is expended in creating these libraries 12 and 22, verifying their equivalence, and maintaining multiple sets of descriptions across various versions of the same IC design. Hand-coding is not only time consuming, but is often error-prone and leads to incomplete modeling. It would be advantageous to reduce the effort required to generate a library within an IC design process to thereby reduce IC design time, reduce cost and increase IC design accuracy.
The main loop in the IC design environment 10 of FIG. 1 consists of: describing the IC design in terms of primitive models from the simulation library 12; verifying through simulation 16a or emulation 16b; and refining and correcting the IC design. In typical CAD design flows, the table-based library 12 is the "golden" (sign-off) simulation library 12 upon which the downstream IC design is based. A large percentage of the library development effort is invested in coding and verifying custom or special function cells that cannot be easily represented by traditional gates such as AND, OR, and are naturally encoded as look-up tables. These look-up tables are called table-based descriptions 14 and are stored in the simulation library 12. The tables 14 are created in the target simulator's language; for example user-defined primitive (UDP) tables in Verilog or VITAL tables in VHDL as described in: IEEE Standards Department, "IEEE Standard VHDL Language Reference Manual," IEEE-1076-1987, IEEE, NY, 1988; IEEE Standards Department, "Verilog Hardware Description Language," IEEE-1364, 1994; and IEEE Standards Department, "Standard VITAL ASIC Modeling Specification," IEEE P1076.4, July 1995.
As shown in FIG. 1, the first library 12 may be used for simulation 16a, emulation 16b and verification 16c, however, an equivalent structural "test" library 22 is needed for test generation 20a and formal verification 20b. The structural library 22 is needed because tools such as test generation 20a and formal verification 20b do not directly accept simulation-table models 14, which would significantly complicate processes such as back-justification and learning. Therefore, the secondary test library 22 is created to support test generation processes 20a and formal verification 20b. Unfortunately, the most engineering-time consuming process of the IC design process 10 is manually translating (e.g., hand-coding) the table-based models 14 (akin to truth-tables) from the simulation library 12 into structural models 24 in the test library 22. The manual translation is labor intensive and error prone and involves explicitly instantiating gates and manually connecting the gates into an equivalent structure. Moreover, once the manually generated structural models 24 are generated, they require verifying their logical equivalence 18, which consumes additional design time. It would be advantageous to make the above IC design process 10 more efficient and cost effective.
Accordingly, what is needed is a system and method for reducing the complexity of an IC design process by eliminating and/or increasing the efficiency of one or more steps of the IC design process. What is also needed is a system and method for reducing the amount of hand-coded descriptions required in the IC design process. In view of the above needs, the present invention provides a system and method for increasing the efficiency of an IC design process to thereby provide a faster, more cost effective and more accurate IC design process. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.